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DATA SHEET
MOS INTEGRATED CIRCUIT
PD178F098
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD178F098 is a flash memory model of the PD178076, 178078, 178096, and 178098, and is provided with a flash memory to/from which data can be written/erased with the microcontroller mounted on a printed circuit board. For the detailed functional description, refer to the following User's Manuals:
PD178078, 178098 Subseries User's Manual: U12790E
78K/0 Series User's Manual - Instruction : U12326E
FEATURES
* Serial interface (UART mode) * IEBusTM controller * Pin-compatible with mask ROM models (except VPP pin) * Flash memory: 60K bytesNote * Internal high-speed RAM: 1024 bytes * Internal extension RAM: 2048 bytesNote * Buffer RAM: 32 bytes * Operable at same supply voltage as mask ROM models (VDD = 4.5 to 5.5 V during PLL operation) Note The capacities of the flash memory and internal extension RAM can be changed using the memory size select register (IMS) and internal extension RAM size select register (IXS). Remark For the differences between the flash memory model and mask ROM models, refer to 1. DIFFERENCES BETWEEN PD178F098 AND MASK ROM MODELS. The electrical specifications (such as supply current) in the PD178F098 differ from those of the mask ROM models. Confirm these differences before mass-producing any application set.
APPLICATION FIELD
Car stereos
ORDERING INFORMATION
Part Number Package 100-pin plastic QFP (14 x 20)
PD178F098GF-3BA
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12920EJ1V0DS00 Date Published June 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1997, 2000
PD178F098
DEVELOPMENT OF 8-BIT DTS SERIES
Models under mass production Models under development
Flash memory model or PROM model
Mask ROM model
80 pins
PD178F048
Internal OSD controller 8-bit PWM x 4 channels 14-bit PWM x 1 channel
80 pins
PD178048 subseries
Internal OSD controller 8-bit PWM x 4 channels 14-bit PWM x 1 channel
100 pins
PD178098 subseries
Internal IEBus controller
100 pins
PD178F098
Internal IEBus controller and UART 100 pins
PD178078 subseries
Internal UART
80 pins
PD178F134
Internal LCD and UART
80 pins
PD178034 subseries
Internal LCD and UART
80 pins
PD178F124
Internal UART
80 pins
PD178024 subseries
Internal UART
80 pins
PD178018A subseries
80 pins
PD178P018A
80 pins
PD178003 subseries
Limits functions of PD178018A subseries
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Data Sheet U12920EJ1V0DS00
PD178F098
FUNCTIONAL OUTLINE
(1/2) Item Internal memory Flash memory 60K bytes Functions
High-speed RAM 1024 bytes Buffer RAM Extension RAM 32 bytes 2048 bytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) * 0.32 s/0.64 s/1.27 s/2.54 s/5.08 s (with crystal resonator of fX = 6.3 MHz) * 0.44 s/0.89 s/1.78 s/3.56 s/7.11 s (with crystal resonator of fX = 4.5 MHz) Note 1 * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test Boolean operation) BCD adjustment, etc. : 80 pins : 8 pins : 64 pins 8 pins
General-purpose register Minimum instruction execution time Instruction set
I/O port
Total * CMOS input * CMOS I/O
* N-ch open-drain output : A/D converter Serial interface 8-bit resolution x 8 channels * * * *
3-wire/SBI/2-wire/I2C busNote 2 mode selectable :1 3-wire mode :1 3-wire mode (with automatic transmit/receive function of up to 32 bytes): 1 UART mode :1
channel channel channel channel
IEBus controller Timer
Provided * * * * Basic timer (timer carry FF (10 Hz)) 16-bit timer/event counter 8-bit timer/event counter Watchdog timer : : : : 1 1 2 1 channel channel channels channel
Buzzer output
BEEP0 pin: 1 kHz, 1.5 kHz, 3 kHz, 4 kHz BUZ pin: 0.77 kHz, 1.54 kHz, 3.08 kHz, 6.15 kHz (with crystal resonator of fX = 6.3 MHz)
Vectored interrupt source PLL frequency synthesizer
Maskable Non-maskable Software Division mode
Internal : 15, External: 8 Internal: 1 1 2 types * Direct division mode (VCOL pin) * Pulse swallow mode (VCOL and VCOH pins)
Reference frequency Charge pump Phase comparator
Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz) Error out output: 2 pins Unlock detectable in software
Notes 1. When using the IEBus controller, the 4.5-MHz crystal resonator cannot be used. Use the 6.3-MHz crystal resonator. 2. When the I2C bus mode is used (including when the mode is implemented in software without using the peripheral hardware), consult NEC when ordering a mask.
Data Sheet U12920EJ1V0DS00
3
PD178F098
(2/2) Item Frequency counter Frequency measurement * AMIFC pin: For 450-kHz counting * FMIFC pin: For 450-kHz/10.7-MHz counting Standby function Reset * HALT mode * STOP mode * * * * * * Reset by RESET pin Internal reset by watchdog timer Reset by power-ON clear circuit Detection of less than 4.5 VNote (Reset does not occur, however.) Detection of less than 3.5 VNote (during CPU operation) Detection of less than 2.3 VNote (in STOP mode) Functions
Supply voltage Package
* VDD = 4.5 to 5.5 V (during CPU, PLL operation) * VDD = 3.5 to 5.5 V (during CPU operation) 100-pin plastic QFP (14 x 20)
Note
These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these.
4
Data Sheet U12920EJ1V0DS00
PD178F098
PIN CONFIGURATION (Top View)
* 100-pin plastic QFP (14 x 20)
PD178F098GF-3BA
GNDPORT VDDPORT P47 P46 P45 P44 P43 P42 P41 P40 P67 P66 P65 P64 P63 P62 P61 P60 GND1 P07/INTP7
P00/INTP0 P01/INTP1 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P70/SI3 P71/SO3 P72/SCK3 P73 P50 P51 P52 P53 P54 P55 P56 P57 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 AVDD P14/ANI4 P15/ANI5 P16/ANI6
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P06/INTP6 P05/INTP5 P04/INTP4 P124 P123 P122 P121/RX0 P120/TX0 P77 P76 P75/TXD0 P74/RXD0 P137 P136 P135 P134 P133 P132 P131/TO51 P130/TO50 P37/BUZ P36/BEEP0 P35/TI51 P34/TI50 P33/TI01 P32/TI00 P31/TO0 P30/VM45 P03/INTP3 P02/INTP2
Cautions 1. Directly connect the VPP pin to GND0, GND1, or GND2 in normal operating mode. 2. Keep the voltage at AVDD, VDDPORT, and VDDPLL same as that at the VDD pin. 3. Keep the voltage at AVSS, GNDPORT, and GNDPLL same as that at GND0, GND1, or GND2. 4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-F capacitor.
P17/ANI7 AVSS REGCPU VDD REGOSC X2 X1 GND0 P100 GND2 P101/AMIFC P102/FMIFC VDDPLL VCOH VCOL GNDPLL EO0 EO1 VPP RESET
Data Sheet U12920EJ1V0DS00
5
PD178F098
Pin Name AMIFC ANI0-ANI7 AVDD AVSS BUSY BEEP0, BUZ EO0, EO1 FMIFC GNDPLL GND0-GND2 INTP0-INTP7 P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P100-P102 P120-P124 P130-P137 REGCPU : AM intermediate frequency counter input : A/D converter input : A/D converter power supply : A/D converter ground : Busy output : Buzzer output : Error out output : FM intermediate frequency counter input : PLL ground : Ground : Interrupt input : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 10 : Port 12 : Port 13 : Regulator for CPU power supply REGOSC RESET RXD0 RX0 SB0, SB1 SCL SDA0, SDA1 SI0, SI1, SI3 SO0, SO1, SO3 STB TI00, TI01 TI50, TI51 TO0 TO50, TO51 TXD0 TX0 VCOL, VCOH VDDPORT VDDPLL VDD VM45 VPP X1, X2 : Regulator for oscillation circuit : Reset input : UART0 serial data input : IEBus serial data input : Serial data bus input/output : Serial clock input/output : Serial data input/output : Serial data input : Serial data output : Strobe output : 16-bit timer capture trigger input : 8-bit timer clock input : 16-bit timer output : 8-bit timer output : UART0 serial data output : IEBus serial data output : Local oscillation input : Port power supply : PLL power supply : Power supply : VDD = 4.5 V monitor output : Programming power supply : Crystal resonator
SCK0, SCK1, SCK3 : Serial clock input/output
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Data Sheet U12920EJ1V0DS00
PD178F098
BLOCK DIAGRAM
TO0/P31 TI00/P32 TI01/P33 TI50/P34 TO50/P130 TI51/P35 TO51/P131
16-bit TIMER/ EVENT COUNTER 8-bit TIMER/ EVENT COUNTER 50 8-bit TIMER/ EVENT COUNTER 51 WATCHDOG TIMER
PORT 0
8
P00-P07
PORT 1
8
P10-P17
PORT 2
8
P20-P27
PORT 3
8
P30-P37
BASIC TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI3/P70 SO3/P71 SCK3/P72 RXD0/P74 TXD0/P75 RX0/P121 TX0/P120 INTP0/P00INTP7/P07 BEEP0/P36 BUZ/P37 RESET X1 X2 VDDPORT GNDPORT VDD 78K/0 CPU CORE FLASH MEMORY (60K bytes)
PORT 4
8
P40-P47
SERIAL INTERFACE 0
PORT 5
8
P50-P57
PORT 6 SERIAL INTERFACE 1
8
P60-P67
PORT 7
8
P70-P77
SERIAL INTERFACE 3
PORT10 RAM (3K bytes)
3
P100-P102
PORT 12
5
P120-P124
UART0 PORT 13 IEBus0 8 A/D CONVERTER ANI0/P10ANI7/P17 AVDD AVSS AMIFC/P101 FMIFC/P102 EO0 EO1 VCOL VCOH VDDPLL GNDPLL IC GND2 8 P130-P137
8
INTERRUPT CONTROL BUZZER OUTPUT RESET CPU PERIPHERAL
FREQUENCY COUNTER
SYSTEM CONTROL
PLL
VM45/P30 REGOSC REGCPU GND0 GND1
VOLTAGE REGULATOR
VOSC VCPU
PLL VOLTAGE REGULATOR
Data Sheet U12920EJ1V0DS00
7
PD178F098
CONTENTS
1. 2.
DIFFERENCES BETWEEN PD178F098 AND MASK ROM MODELS ..................................... 9 PIN 2.1 2.2 2.3 FUNCTION LIST ...................................................................................................................... 10 Port Pins .................................................................................................................................. 10 Pins Other Than Port Pins ...................................................................................................... 11 I/O Circuits of Pins and Recommended Connections of Unused Pins ............................. 13
3. 4. 5. 6.
MEMORY SIZE SELECT REGISTER (IMS) ................................................................................. 17 INTERNAL EXTENSION RAM SIZE SELECT REGISTER (IXS) .............................................. 18 INTERRUPT FUNCTION ................................................................................................................. 19 FLASH MEMORY PROGRAMMING .............................................................................................. 6.1 Selecting Communication Mode ........................................................................................... 6.2 Flash Memory Programming Function ................................................................................. 6.3 Connecting Flashpro III .......................................................................................................... 23 23 24 25
7. 8. 9.
ELECTRICAL SPECIFICATIONS ................................................................................................... 26 PACKAGE DRAWING ..................................................................................................................... 44 RECOMMENDED SOLDERING CONDITIONS ............................................................................. 45
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 46 APPENDIX B. RELATED DOCUMENTS .............................................................................................. 48
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Data Sheet U12920EJ1V0DS00
PD178F098
1. DIFFERENCES BETWEEN PD178F098 AND MASK ROM MODELS
The PD178F098 is provided with a flash memory to/from which data can be written/erased with the device mounted on a printed circuit board. The differences between the flash memory model (PD178F098) and mask ROM models (PD178076, 178078, 178096, and 178098) are shown in Table 1-1. Table 1-1. Differences between PD178F098 and Mask ROM Models
Item Internal memory ROM structure ROM capacity External extension RAM Internal ROM capacity selected by memory size select register (IMS) Internal extension RAM capacity selected by internal extension RAM size select register (IXS) Serial interface Equivalent to mask ROM model Equivalent to mask ROM model 4 * * * *
PD178F098
Flash memory 60K bytes 2048 bytes
PD178076, 178078
Mask ROM
PD178096, 178098 PD178096: 48K bytes PD178098: 60K bytes PD178096: 1024 bytes PD178098: 2048 bytes PD178096: CCH PD178098: CFH PD178096: 0AH PD178098: 08H
3 channels * 3-wire/SBI/2-wire/I2C bus mode selectable * 3-wire (with automatic transmit/receive function) * 3-wire Provided 21
PD178076: 48K bytes PD178078: 60K bytes PD178076: 1024 bytes PD178078: 2048 bytes PD178076: CCH PD178078: CFH PD178076: 0AH PD178078: 08H
channels 3-wire/SBI/2-wire/I2C bus mode selectable 3-wire (with automatic transmit/receive function) 3-wire UART Not provided 22 Provided Not provided
IEBus controller Interrupt source IC pin VPP pin Electrical specifications and recommended soldering conditions
Provided 24 Not provided Provided See the relevant data sheet
Caution The noise resistance and noise radiation differ between flash memory versions and mask ROM versions. When considering the replacement of flash memory versions with mask ROM versions in the process from trial manufacturing to mass production, adequate evaluation should be carried out using CS products (not ES products) of mask ROM versions.
Data Sheet U12920EJ1V0DS00
9
PD178F098
2. PIN FUNCTION LIST 2.1 Port Pins (1/2)
Pin Name P00-P07 I/O I/O Port 0. 8-bit I/O port. Can be set in input or output mode in 1-bit units. P10-P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40-47 I/O Port 4. 8-bit I/O port. Can be set in input or output mode in 1-bit units. P50-P57 I/O Port 5. 8-bit I/O port. Can be set in input or output mode in 1-bit units. P60-P67 I/O Port 6. 8-bit I/O port. Can be set in input or output mode in 1-bit units. P70 P71 P72 P73 P74 P75 P76, P77 RXD0 TXD0 - I/O Port 7. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Input SI3 SO3 SCK3 - Input - Input - Input I/O Port 3. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Input Input I/O Port 1. 8-bit input port. Port 2. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Input Input ANI0-ANI7 SI1 SO1 SCK1 STB BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL VM45 TO0 TI00 TI01 TI50 TI51 BEEP0 BUZ - Function At Reset Input Shared by: INTP0-INTP7
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Data Sheet U12920EJ1V0DS00
PD178F098
2.1 Port Pins (2/2)
Pin Name P100 P101 P102 P120 P121 P122-P124 P130 P131 P132-P137 Output I/O I/O I/O Port 10. 3-bit I/O port. Can be set in input or output mode in 1-bit units. Port 12. 5-bit I/O port. Can be set in input or output mode in 1-bit units. Port 13. 8-bit output port. N-ch open-drain output port (15 V withstand) Low-level output TO50 TO51 - Input Function At Reset Input AMIFC FMIFC TX0 RX0 - Shared by: -
2.2 Pins Other Than Port Pins (1/2)
Pin Name INTP0-INTP7 I/O Input Function External maskable interrupt input whose valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. SI0 SI1 SI3 SO0 SO1 SO3 SB0 SB1 SDA0 SDA1 SCK0 SCK1 SCK3 SCL STB Output N-ch open drain I/O Strobe output for serial interface automatic transmission/ reception. BUSY Input Busy input for serial interface automatic transmission/ reception. VW45 TI00 TI01 TI50 TI51 TO0 TO50 TO51 BEEP0 BUZ Output Output Input External count clock input to 8-bit timer (TM50). External count clock input to 8-bit timer (TM51). 16-bit timer (TM0) output. 8-bit timer (TM50) output. 8-bit timer (TM51) output. Buzzer output. Input Low-level output Input Input Output Input VDD = 4.5 V monitor output External count clock input to 16-bit timer (TM0). Input Input P30 P32 P33 P34 P35 P31 P130 P131 P36 P37 Input P24 Input I/O Serial clock input/output to/from serial interface. Input I/O Serial data input/output to/from serial interface. N-ch open drain I/O Input Output Serial data output from serial interface. Input Input Serial data input to serial interface. Input P25/SB0/SDA0 P20 P70 P26/SB1/SDA1 P21 P71 P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 P27/SCL P22 P72 P27/SCK0 P23 At Reset Input Shared by: P00-P07
Data Sheet U12920EJ1V0DS00
11
PD178F098
2.2 Pins Other Than Port Pins (2/2)
Pin Name ANI0-ANI7 EO0, EO1 I/O Input Output Function Analog input to A/D converter. Error out output from charge pump of PLL frequency synthesizer. VCOL Input Inputs local oscillation frequency of PLL (in HF and MF modes). VCOH AMIFC FMIFC Input Input Input Inputs local oscillation frequency of PLL (in VHF mode). Input to AM intermediate frequency counter. Input to FM intermediate frequency or AM intermediate frequency counter. RXD0 TXD0 Input Output Serial data input to asynchronous serial interface (UART0). Serial data output from asynchronous serial interface (UART0). TX0 RX0 RESET X1 X2 REGOSC Output Input Input Input - - Regulator for oscillation circuit. Connect this pin to GND via 0.1-F capacitor. REGCPU - Regulator for CPU power supply. Connect this pin to GND via 0.1-F capacitor. VDD GND0-GND2 VDDPORT GNDPORT AVDD - - - - - Positive power supply. Ground. Port power supply. Port ground. A/D converter positive power supply. Keep voltage at this pin same as that at VDD0. AVSS VDDPLL Note GNDPLLNote VPP - A/D converter ground. Keep voltage at this pin same as that at GND0 through GND2. - - - PLL positive power supply. PLL ground. Pin to apply high voltage at program writing/verifying. Directly connect this pin to GND0, GND1, or GND2 in normal operating mode. - - - - - - - - - - - - - - - - - - - - IEBus controller data output. IEBus controller data input. System reset input. Connection of crystal resonator for system clock oscillation. Input Input - - - - P120 P121 - - - - Input Input P74 P75 - Input Input P101 P102 - - - At Reset Input - Shared by: P10-P17 -
Note
Connect a capacitor of about 1000 pF between the VDDPLL and GNDPLL pins.
12
Data Sheet U12920EJ1V0DS00
PD178F098
2.3 I/O Circuits of Pins and Recommended Connections of Unused Pins
Table 2-1 shows the types of the I/O circuits of the respective pins and the recommended connections of the pins when they are not used. For the configuration of the I/O circuit of each pin, refer to Figure 2-1. Table 2-1. I/O Circuit Type of Each Pin (1/2)
Pin Name P00/INTP0-P07/INTP7 I/O Circuit Type 8 I/O I/O Recommended Connection of Unused Pin Input: Connect each of them to VDD, VDDPORT, GND0 to GND2, or GNDPORT via resistor. Output: Leave open. Connect these pins to VDD, VDDPORT, GND0 to GND2 or GNDPORT. Input: Connect each of them to VDD, VDDPORT, GND0 to GND2, or GNDPORT via resistor. Output: Leave open.
P10/ANI0-P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/VM45 P31/TO0 P32/TI00 P33/TI01 P34/TI50 P35/TI51 P36/BEEP0 P37/BUZ P40-P47 P50-P57 P60-P67 P70/SI3 P71/SO3 P72/SCK3 P73 P74/RXD0 P75/TXD0 P76, P77 P100 P101/AMIFC P102/FMIFC P120/TX0 P121/RX0 P122-P124
25 5-K 5 5-K 5 5-K 10-D
Input I/O
5
5-K
5
5-K 5 5-K 5 5-K 5
5-K 5
Data Sheet U12920EJ1V0DS00
13
PD178F098
Table 2-1. I/O Circuit Type of Each Pin (2/2)
Pin Name P130/TO50 P131/TO51 P132-P137 EO0 EO1 VCOL, VCOH REGOSC, REGCPU RESET AVDD AVSS VPP 2 - DTS-AMP2 - Input - Input - Disable PLL in software and select pull-down. Connect these pins to GND0, GND1, or GND2 via 0.1-F capacitor. - Connect this pin to VDD or VDDPORT. Directly connect these pins to GND0 to GND2, or GNDPORT. DTS-EO1 I/O Circuit Type 19 I/O Output Recommended Connection of Unused Pin Open these pins.
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Data Sheet U12920EJ1V0DS00
PD178F098
Figure 2-1. I/O Circuits of Respective Pins (1/2)
Type 2 Type 5 VDD data P-ch IN/OUT IN output disable input enable N-ch
Schmitt trigger input with hysteresis characteristics
Type 5-K VDD data
Type 8
VDD P-ch IN/OUT IN/OUT data P-ch
output disable
N-ch
output disable
N-ch
input enable
Type 10-D VDD data P-ch IN/OUT open drain output disable N-ch
Type 19
OUT N-ch
input enable
Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as VDDPORT and GNDPORT.
Data Sheet U12920EJ1V0DS00
15
PD178F098
Figure 2-1. I/O Circuits of Respective Pins (2/2)
Type 25
Type DTS-EO1
VDDPLL P-ch Comparator
+ -
DW IN
P-ch OUT
N-ch VREF (Threshold voltage)
input enable
UP
N-ch GNDPLL
Type DTS-AMP
VDDPLL
IN
Note GNDPLL
Note
This switch is selectable in software only for the VCOL and VCOH pins.
Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as VDDPORT and GNDPORT.
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Data Sheet U12920EJ1V0DS00
PD178F098
3. MEMORY SIZE SELECT REGISTER (IMS)
The internal memory capacity of the PD178F098 can be changed using the memory size select register (IMS). By using this register, the memory of the PD178F098 can be mapped in the same manner as a mask ROM model with a different internal memory capacity. Use an 8-bit memory manipulation instruction to set the IMS. This register is set to CFH at reset. Figure 3-1. Format of Memory Size Select Register (IMS)
Symbol 7 6 5 4 0 3 2 1 0 Address FFF0H At reset CFH R/W R/W
IMS RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
RAM2 1 Others
RAM1 RAM0 1 0 1024 bytes Setting prohibited RAM1 0 1 RAM0 0 1 48K bytes 60K bytes
Selects internal high-speed RAM capacity
RAM3 RAM2 1 1 Others 1 1
Selects internal ROM capacity
Setting prohibited
Table 3-1 shows the setting of IMS to perform the same memory mapping as that of a mask ROM model. Table 3-1. Setting of Memory Size Select Register
Targeted Model Setting of IMS CCH CFH
PD178076, 178096 PD178078, 178098
Data Sheet U12920EJ1V0DS00
17
PD178F098
4. INTERNAL EXTENSION RAM SIZE SELECT REGISTER (IXS)
The internal extention RAM capacity of the PD178F098 can be changed using the internal extention RAM size select register (IXS). By using this register, the memory of the PD178F098 can be mapped in the same manner as a mask ROM model with a different internal extention RAM capacity. Use an 8-bit memory manipulation instruction to set the IXS. This register is set to 0CH at reset. Figure 4-1. Format of Internal Extension RAM Size Select Register (IXS)
Symbol IXS 7 0 6 0 5 0 4 3 2 1 0 Address FFF4H At reset 0CH R/W R/W
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 0 0 Others 1 1 0 0 0 1 0 0 2048 bytes 1024 bytes
Selects internal extension RAM capacity
Setting prohibited
Table 4-1 shows the setting of IXS to perform the same memory mapping as that of a mask ROM model. Table 4-1. Setting of Internal RAM Size Select Register
Targeted Model Setting of IXS 0AH 08H
PD178076, 178096 PD178078, 178098
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Data Sheet U12920EJ1V0DS00
PD178F098
5. INTERRUPT FUNCTION
The PD178F098 has the following three types and 24 sources of interrupts: * Non-maskable : 1Note * Maskable * Software Note : 23Note :1
Two types of watchdog interrupt sources (INTWDT), non-maskable and maskable, are available, and either of them can be selected. Table 5-1. Interrupt Sources (1/2)
Interrupt Source Name INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTCSI0 INTCSI1 INTCSI3 INTTM50 INTTM51 INTSER0 INTSR0 INTST0 INTBTM0 End of transfer by serial interface 0 End of transfer by serial interface 1 End of transfer by serial interface 3 Generation of coincidence signal of 8-bit timer/event counter 50 Generation of coincidence signal of 8-bit timer/event counter 51 Reception error of serial interface UART0 End of reception by serial interface UART0 End of transmission by serial interface UART0 Generation of coincidence signal of basic timer Internal Trigger Overflow of watchdog timer (when watchdog timer mode 1 is selected) Overflow of watchdog timer (when interval timer mode is selected) Pin input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H (B) Vector Basic Table Configuration Address TypeNote 2 0004H (A) (B) (C)
Default Interrupt Type PriorityNote 1 Non-maskable Maskable - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Internal/ External Internal
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending according to their default priorities. The default priority 0 is the highest, while 22 is the lowest. 2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 5-1.
Data Sheet U12920EJ1V0DS00
19
PD178F098
Table 5-1. Interrupt Sources (2/2)
Default Interrupt Type PriorityNote 1 Maskable 18 Interrupt Source Name INTTM00 Trigger Generation of signal indicating coincidence between 16-bit timer counter (TM0) and capture/compare register (CR00) (when CR00 is used as compare register) Detection of input edge of TI00/P32 pin (when CR00 is used as capture register) 19 INTTM01 Generation of signal indicating coincidence between 16-bit timer counter (TM0) and capture/compare register (CR01) (when CR01 is used as compare register) Detection of input edge of TI01/P33 pin (when CR01 is used as capture register) 20 21 22 Software - INTIE1 INTIE2 INTAD BRK IEBus0 data access request IEBus0 communication error and start/end of communication End of conversion by A/D converter AD1 Execution of BRK instruction - Internal/ External Internal Vector Basic Table Configuration Address Type Note 2 0028H (B)
External Internal 002AH
(D) (B)
External Internal 002CH 002EH 0030H 003EH
(D) (B)
(B) (E)
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending according to their default priorities. The default priority 0 is the highest, while 22 is the lowest. 2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 5-1.
20
Data Sheet U12920EJ1V0DS00
PD178F098
Figure 5-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generation circuit
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority control circuit
Vector table address generation circuit Standby release signal
(C) External maskable interrupt (INTP0 through INTP7)
Internal bus
External interrupt rising/falling edge enable registers (EGP, EGN)
MK
IE
PR
ISP
Interrupt request
Edge detection circuit
IF
Priority control circuit
Vector table address generation circuit Standby release signal
Data Sheet U12920EJ1V0DS00
21
PD178F098
Figure 5-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupts (INTTM00, INTTM01)
Internal bus
Prescaler mode register (PRM0)
MK
IE
PR
ISP
Interrupt request
Edge detection circuit
IF
Priority control circuit
Vector table address generation circuit Standby release signal
(E) Software interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generation circuit
Remark IF : Interrupt request flag IE : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag
22
Data Sheet U12920EJ1V0DS00
PD178F098
6. FLASH MEMORY PROGRAMMING
The program memory provided in the PD178F098 is flash memory. The flash memory can be written on-board, i.e., with the PD178F098 mounted on the target system. To do so, connect a dedicated flash writer (Flashpro III (Part number FL-PR3, PG-FP3)) to the host machine and target system. Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.
6.1 Selecting Communication Mode
The flash memory is written by using Flashpro III and by means of serial communication. Select a communication mode from those listed in Table 6-1. To select a communication mode, the format shown in Figure 6-1 is used. Each communication mode is selected depending on the number of VPP pulses shown in Table 6-1. Table 6-1. Communication Modes
Communication Mode 3-wire serial I/O (SIO3) Number of Channels 1 SI3/P70 SO3/P71 SCK3/P72 UART0 1 RXD0/P74 TXD0/P75 8 Pins Used Number of VPP Pulses 0
Caution Be sure to select a communication mode by the number of VPP pulses shown in Table 6-1. Figure 6-1. Communication Mode Selection Format
VPP pulse 10 V VPP VDD GND VDD RESET GND Flash memory writing mode
Data Sheet U12920EJ1V0DS00
23
PD178F098
6.2 Flash Memory Programming Function
An operation such as writing the flash memory is performed when a command or data is transmitted/received in the selected communication mode. The major flash memory programming functions are listed in Table 6-2. Table 6-2. Major Flash Memory Programming Functions
Function Batch erase Batch blank check Data write Batch verify Erases all memory contents. Checks erased status of entire memory. Writes data to flash memory starting from write start address and based on number of data (bytes) to be written). Compares all contents of memory with input data. Description
24
Data Sheet U12920EJ1V0DS00
PD178F098
6.3 Connecting Flashpro III
Connection with Flashpro III differs depending on the communication mode (3-wire serial I/O or UART0). Figures 6-2 and 6-3 show the connection in the respective modes. Figure 6-2. Connection of Flashpro III in 3-Wire Serial I/O Mode
Flashpro III VPP VDD RESET CLK SCK SO SI GND VPP VDD RESET X1 SCK3 SI3 SO3 GND
PD178F098
Figure 6-3. Connection of Flashpro III in UART0 Mode
Flashpro III VPP VDD RESET CLK SO SI GND VPP VDD RESET X1 RXD0 TXD0 GND
PD178F098
Data Sheet U12920EJ1V0DS00
25
PD178F098
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD VDDPORT AVDD VDDPLL VPP Input voltage Output voltage Output breakdown voltage Analog input voltage High-level output current VAN IOH P10-P17 1 pin Total of P00-P01, P20-P27, P50-P57, and P70-P73 Total of P02-P07, P30-P37, P40-P47, P60-P67, P74-P77, and P120-P124 Total of P100-P102 Low-level output current Total of P00-P01, P20-P27, P50-P57, and P70-P73 Total of P02-P07, P30-P37, P40-P47, P60-P67, P74-P77, P120-P124, and P130-P137 Total of P100-102 Peak value r.m.s Operating temperature TA During normal operation During flash memory programming Storage temperature Tstg 20 10 -40 to +85 10 to 40 -55 to +125 mA mA C C C IOL Note 2 1 pin Peak value r.m.s Peak value r.m.s Peak value r.m.s -10 16 8 30 15 30 15 mA mA mA mA mA mA mA Analog input pin -0.3 to VDD + 0.3 -8 -15 -15 V mA mA mA VI VO VBDS Excluding P130 to P137 P130-P137 N-ch open drain Conditions Rating -0.3 to +6.0 -0.3 to VDD + 0.3 Note 1 Unit V V V V V V V V
-0.3 to VDD + 0.3 Note 1 -0.3 to VDD + 0.3 Note 1 -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 16
Notes 1. Keep the voltage at VDDPORT, AVDD, and VDDPLL same as that at the VDD pin. 2. Calculate the r.m.s as follows: [r.m.s] = [Peak value] x Duty Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. Be sure to use the product with these ratings never being exceeded. Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin.
26
Data Sheet U12920EJ1V0DS00
PD178F098
Recommended Supply Voltage Ranges (TA = -40 to +85C)
Parameter Supply voltage Symbol VDD1 VDD2 Data retention voltage Output breakdown voltage VDDR VBDS Conditions When CPU and PLL are operating When CPU is operating and PLL is stopped When crystal oscillation stops P130-P137 (N-ch open drain) MIN. 4.5 3.5 2.3 TYP. 5.0 5.0 MAX. 5.5 5.5 5.5 15 Unit V V V V
DC Characteristics (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter High-level input voltage Symbol VIH1 Test Conditions P10-P17, P21, P23, P30, P31, P36, P37, P40-P47, P50-P57, P60-P67, P71, P73, P75-P77, P100-P102, P120, P122-P124 P00-P07, P20, P22, P24-P27, P32-P35, P70, P72, P74, P121, RESET P10-P17, P21, P23, P30, P31, P36, P37, P40-P47, P50-P57, P60-P67, P71, P73, P75-P77, P100-P102, P120, P122-P124 P00-P07, P20, P22, P24-P27, P32-P35, P70, P72, P74, P121, RESET P00-P07, P20-P24, P30-P37, 4.5 V VDD 5.5 V, P40-P47, P50-P57, P60-P67, IOH = -1 mA P70-P77, P100-P102, 3.5 V VDD < 4.5 V, P120-P124 IOH = -100 A EO0, EO1 VDD = 4.5 to 5.5 V, IOH = -3 mA MIN. 0.7 VDD TYP. MAX. VDD Unit V
VIH2
0.8 VDD
VDD
V
Low-level input voltage
VIL1
0
0.3 VDD
V
VIL2
0
0.2 VDD
V
High-level output voltage
VOH1
VDD - 1.0
V
VDD - 0.5
V
VOH2
VDD - 1.0
V
Low-level output voltage
VOH1
P00-P07, P20-P27, P30-P37, 4.5 V VDD 5.5 V, P40-P47, P50-P57, P60-P67, IOL = 1 mA P70-P77, P100-P102, 3.5 V VDD < 4.5 V, P120-P124, P130-P137, IOL = 100 A EO0, EO1 VDD = 4.5 to 5.5 V, IOL = 3 mA VI = VDD
1.0
V
0.5
V
VOL2
1.0
V
High-level input leakage current
ILIH
P00-P07, P10-P17, P20-P24, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P100-P102, P120-P124, RESET
3
A
Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin.
Data Sheet U12920EJ1V0DS00
27
PD178F098
DC Characteristics (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter Low-level input leakage current Symbol ILIL Conditions P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P100-P102, P120-P124, RESET P130-P137 P130-P137 P25-P27 (at N-ch open drain I/O) P25-P27 (at N-ch open drain I/O) EO0, EO1 EO0, EO1 When CPU is operating and PLL is stopped. Sine wave input to X1 pin VI = VDD In HALT mode with PLL stopped. Sine wave input to X1 pin VI = VDD VI = 0 V MIN. TYP. MAX. -3 Unit
A
Output off leakage current
ILOH1 ILOL1 ILOH2
VO = 15 V VO = 0 V VO = VDD
-3 3 -3
A A A A A A
mA
ILOL2
VO = 0 V
3
ILOH3 ILOL3 Supply currentNote IDD1
VO = VDD VO = 0 V fx = 4.5 MHz 5.0
-3 3 18
IDD2
fx = 6.3 MHz
7.0
20
mA
IDD3
fx = 4.5 MHz
0.3
0.8
mA
IDD4
fx = 6.3 MHz
0.4
1.0
mA
Data retention voltage
VDDR1 VDDR2
When crystal resonator is oscillating When crystal oscillation is stopped Power-failure detection function Data memory retained When crystal oscillation is stopped TA = 25C, VDD = 5 V
3.5 2.2
5.5
V V
VDDR3 Data retention current IDDR1
2.0 2.0 4.0
V
A A
IDDR2
2.0
20
Note
Excluding AVDD current and VDDPLL current.
Remarks 1. fX: System clock oscillation frequency 2. Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin.
28
Data Sheet U12920EJ1V0DS00
PD178F098
Reference Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter Supply current Symbol IDD5 Conditions When CPU and PLL are operating. Sine wave input to VCOH pin At fIN = 160 MHz, VIN = 0.15 VP-P MIN. TYP. 8 MAX. Unit mA
AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter Cycle time (minimum instruction execution time) TI00, TI01 input high-/low-level widths TI50, TI51 input frequency TI50, TI51 input high-/low-level widths Interrupt input high-/low-level widths RESET pin low-level width tTIH5, tTIL5 200 ns tTIH0, tTIL0 Symbol TCY At fX = 6.3 MHz At fX = 4.5 MHzNote 1 Conditions MIN. 0.32 0.44 TYP. MAX. 5.08 7.11 Unit
s s
4/fsamNote 2
s
fTI5
2
MHz
tINTH, tINTL
INTP0-INTP7
1
s
tRSL
10
s
Notes 1. Only when products not using IEBus are supported. 2. fsam = fX/2, fX/4, fX/64 selectable by bits 0 and 1 (PRM00 and PRM01) of the prescaler mode register 0 (PRM0). However, fsam = fX/8 when the valid edge of TI00 is selected as the count clock.
Data Sheet U12920EJ1V0DS00
29
PD178F098
(2) Serial interface (TA = -40 to +85C, VDD = 3.5 to 5.5 V) (a) Serial interface 0 (i) 3-wire serial I/O mode (SCK0 ... internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Test Conditions VDD = 4.5 to 5.5 V MIN. 800 1600 SCK0 high-/low-level width tKH1, tKL1 SI0 setup time (to SCK0) tSIK1 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKCY1/2 - 50 tKCY1/2 - 100 100 150 SI0 hold time (from SCK0) SO0 output delay time from SCK0 tKSI1 tKSO1 C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns
400 300
ns
Note
C is the load capacitance of SCK0 and SO0 output line. (ii) 3-wire serial I/O mode (SCK0 ... external clock input)
Parameter Symbol tKCY2 Test Conditions VDD = 4.5 to 5.5 V MIN. 800 1600 TYP. MAX. Unit ns ns ns ns ns ns 300 1000 ns ns
SCK0 cycle time
SCK0 high-/low-level width
tKH2, tKL2
VDD = 4.5 to 5.5 V
400 800 100 400
SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 at rising or falling edge time
tSIK2 tKSI2 tKSO2 tR2, tF2 C = 100 pF
Note
Note
C is the load capacitance of SO0 output line.
30
Data Sheet U12920EJ1V0DS00
PD178F098
(iii) SBI mode (SCK0 ... internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK0 high-/low-level width tKH3, tKL3 SB0, SB1 setup time (to SCK0) tSIK3 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKCY3/2 - 50 tKCY3/2 - 150 100 300 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKSB tSBK tSBH tSBL tKSI3 tKSO3 R = 1 k C = 100 pF Note VDD = 4.5 to 5.5 V tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line. (iv) SBI mode (SCK0 ... external clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK0 high-/low-level width tKH4, tKL4 SB0, SB1 setup time (to SCK0) tSIK4 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V 400 1600 100 300 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 at rising or falling edge time tKSB tSBK tSBH tSBL tR4, tF4 tKSI4 tKSO4 R = 1 k C = 100 pF Note VDD = 4.5 to 5.5 V tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 1000 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
Data Sheet U12920EJ1V0DS00
31
PD178F098
(v) 2-wire serial I/O mode (SCK0 ... internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY5 tKH5 tKL5 Test Conditions R = 1 k C = 100 pF
Note
MIN. 1600 tKCY5/2 - 160
TYP.
MAX.
Unit ns ns ns ns ns ns ns
VDD = 4.5 to 5.5 V
tKCY5/2 - 50 tKCY5/2 - 100
SB0, SB1 setup time (to SCK0)
tSIK5
VDD = 4.5 to 5.5 V
300 350
SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0
tKSI5 tKSO5
600 0 300
ns
Note
R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line. (vi) 2-wire serial I/O mode (SCK0 ... external clock input)
Parameter Symbol tKCY6 tKH6 tKL6 tSIK6 tKSI6 tKSO6 R = 1 k C = 100 pF tR6, tF6
Note
Test Conditions
MIN. 1600 650 800 100 tKCY6/2
TYP.
MAX.
Unit ns ns ns ns ns
SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 at rising or falling edge time
VDD = 4.5 to 5.5 V
0 0
300 500 1000
ns ns ns
Note
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
32
Data Sheet U12920EJ1V0DS00
PD178F098
(vii) I 2C Bus mode (SCL ... internal clock output)
Parameter SCL cycle time SCL high-level width SCL low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time (from SCL) SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width tKSB Symbol tKCY7 tKH7 tKL7 tSIK7 tKSI7 Test Conditions R = 1 k C = 100 pF
Note
MIN. 10 tKCY7 - 160 tKCY7 - 50 200 0
TYP.
MAX.
Unit
s
ns ns ns ns
tKSO7
VDD = 4.5 to 5.5 V
0 0 200
300 500
ns ns ns
tSBK tSBH
400 500
ns ns
Note
R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line. (viii) I2 C Bus mode (SCL ... external clock input)
Parameter Symbol tKCY8 tKH8, tKL8 tSIK8 tKSI8 Test Conditions MIN. 1000 400 200 0 TYP. MAX. Unit ns ns ns ns
SCL cycle time SCL high-/low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width SCL at rising or falling edge time
tKSO8
R = 1 k C = 100 pF
Note
VDD = 4.5 to 5.5 V
0 0 200
300 500
ns ns ns
tKSB
tSBK tSBH tR8, tF8
400 500 1000
ns ns ns
Note
R and C are the load resistance and load capacitance of SDA0 and SDA1 output line.
Data Sheet U12920EJ1V0DS00
33
PD178F098
(b) Serial interface 1 (i) 3-wire serial I/O mode (SCK1 ... internal clock output)
Parameter SCK1 cycle time SCK1 high/low-level width Symbol tKCY9 tKH9, tKL9 tSIK9 tKSI9 tKSO9 C = 100 pF Note Test Conditions MIN. 800 tKCY9/2 - 50 TYP. MAX. Unit ns ns
SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1)
100 400 300
ns ns ns
Note
C is the load capacitance of SCK1 and SO1 output line. (ii) 3-wire serial I/O mode (SCK1 ... external clock input)
Parameter Symbol tKCY10 tKH10, tKL10 tSIK10 tKSI10 tKSO10 C = 100 pF Note Test Conditions MIN. 800 400 TYP. MAX. Unit ns ns
SCK1 cycle time SCK1 high/low-level width
SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1)
100 400 300 1000
ns ns ns ns
SCK1 at rising or falling edge time tR10, tF10
Note
C is the load capacitance of SO1 output line.
34
Data Sheet U12920EJ1V0DS00
PD178F098
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock output)
Parameter SCK1 cycle time SCK1 high/low-level width Symbol tKCY11 tKH11, tKL11 tSIK11 tKSI11 tKSO11 tSBD tSBW tBYS C = 100 pF Note tKCY11/2 - 100 tKCY11/2 - 30 100 Test Conditions MIN. 800 tKCY11/2 - 50 TYP. MAX. Unit ns ns
SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1) STB from SCK1 Strobe signal high-level width Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) SCK1 from busy inactive
100 400 300 tKCY11/2 + 100 tKCY11/2 + 30
ns ns ns ns ns ns
tBYH
100
ns
tSPS
200
ns
Note
C is the load capacitance of SO1 output line. (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock input)
Parameter Symbol tKCY12 tKH12, tKL12 tSIK12 tKSI12 tKSO12 C = 100 pF Note Test Conditions MIN. 800 400 TYP. MAX. Unit ns ns
SCK1 cycle time SCK1 high/low-level width
SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1)
100 400 300 1000
ns ns ns ns
SCK1 at rising or falling edge time tR12, tF12
Note
C is the load capacitance of SO1 output line.
Data Sheet U12920EJ1V0DS00
35
PD178F098
(c) Serial interface 3 (i) 3-wire serial I/O mode (SCK3 ... internal clock output)
Parameter SCK3 cycle time SCK3 high/low-level width Symbol tKCY13 tKH13, tKL13 tSIK13 tKSI13 tKSO13 C = 100 pF Note Test Conditions MIN. 800 tKCY13/2 - 50 TYP. MAX. Unit ns ns
SI3 setup time (to SCK3) SI3 hold time (from SCK3) SO3 output delay time (from SCK3)
100 400 300
ns ns ns
Note
C is the load capacitance of SCK3 and SO3 output line. (ii) 3-wire serial I/O mode (SCK3 ... external clock input)
Parameter Symbol tKCY14 tKH14, tKL14 tSIK14 tKSI14 tKSO14 C = 100 pF Note Test Conditions MIN. 800 400 TYP. MAX. Unit ns ns
SCK3 cycle time SCK3 high/low-level width
SI3 setup time (to SCK3) SI3 hold time (from SCK3) SO3 output delay time (from SCK3)
100 400 300 1000
ns ns ns ns
SCK3 at rising or falling edge time tR14, tF14
Note
C is the load capacitance of SO3 output line.
(d) Serial interface UART0 (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Test Conditions MIN. TYP. MAX. 38400 Unit bps
36
Data Sheet U12920EJ1V0DS00
PD178F098
AC Timing Test Point (Excluding X1 Input)
0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD
Test Points
TI Timing
tTIL0 tTIH0
TI00, TI01
1/fTI5 tTIL5 tTIH5
TI50,TI51
Interrupt Input Timing
tINTL tINTH
INTP0 to INTP7
RESET Input Timing
tRSL
RESET
Data Sheet U12920EJ1V0DS00
37
PD178F098
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tRn SCK0, SCK1, SCK3 tSIKm tKSIm tKHm tFn
SI0, SI1, SI3 tKSOm
Input Data
SO0, SO1, SO3
Output Data
Remark m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14 SBI mode (bus release signal transfer):
tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 tF4
SB0, SB1 tKSO3, 4
38
Data Sheet U12920EJ1V0DS00
PD178F098
SBI mode (command signal transfer):
tKCY3, 4 tKL3, 4 tR4 tKH3, 4 tF4
SCK0 tSIK3, 4 tKSB tSBK tKSI3, 4
SB0, SB1 tKSO3, 4
2-wire serial I/O mode:
tKCY5, 6 tKL5, 6 tR6 SCK0 tSIK5, 6 tKSO5, 6 SB0, SB1 tKSI5, 6 tKH5, 6 tF6
I 2C bus mode:
tF8 SCL tKL7, 8 tKSI7, 8 tKH7, 8 tSIK7, 8 tKSO7, 8 tR8
tKCY7, 8 tKSB tSBK tKSB
SDA0, SDA1 tSBH tSBK
Data Sheet U12920EJ1V0DS00
39
PD178F098
3-wire serial I/O mode with automatic transmit/receive function:
SO1
D2
D1
D0
D7
SI1
D2 tSIK11, 12 tKSO11, 12
D1
D0 tKSI11, 12 tKH11, 12 tF12
D7
SCK1 tR12 tKL11, 12 STB tKCY11, 12 tSBD tSBW
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
8
9 Note
10 Note tBYS
10 + n Note tBYH tSPS
1
BUSY (Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
IEBus Controller Characteristics (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter IEBus system clock frequency Symbol fs Fixed to mode 1 Conditions MIN. TYP. 6.3Note MAX. Unit MHz
Note
Although the system clock frequency is 6.0 MHz in the IEBus standard, in these products, normal operation is guaranteed at 6.3 MHz.
Remark 6.0 MHz and 6.3 MHz cannot both be used as the IEBus system clock frequency.
40
Data Sheet U12920EJ1V0DS00
PD178F098
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 3.5 to 5.5 V)
Parameter Resolution Total conversion errorNotes 1, 2 Conversion time Analog input voltage tCONV VIAN 15.2 0 VDD = 4.5 to 5.5 V Symbol Conditions MIN. 8 TYP. 8 MAX. 8 1.0 1.4 45.7 VDD Unit bit %FSR %FSR
s
V
Notes 1. Excluding quantization error (0.2%FSR) 2. This value is indicated as a ratio to the full-scall value. PLL Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter Operating frequency Symbol fIN1 fIN2 fIN3 fIN4 Conditions VCOL pin, MF mode, sine wave input, VIN = 0.15 VP-P VCOL pin, HF mode, sine wave input, VIN = 0.15 VP-P VCOH pin, VHF mode, sine wave input, VIN = 0.15 VP-P VCOH pin, VHF mode, sine wave input, VIN = 0.3 VP-P MIN. 0.5 10 60 40 TYP. MAX. 3.0 40 130 160 Unit MHz MHz MHz MHz
Remark The above values are the result of NEC's evaluation of the device. If the device is likely to be affected by noise in your application, it is recommended to use the device at a voltage higher than the above values. IFC Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter Operating frequency Symbol fIN5 Conditions AMIFC pin, AMIF count mode, sine wave input, VIN = 0.15 VP-P FMIFC pin, FMIF count mode, sine wave input, VIN = 0.15 VP-P FMIFC pin, AMIF count mode, sine wave input, VIN = 0.15 VP-P MIN. 0.4 TYP. MAX. 0.5 Unit MHz
fIN6
10
11
MHz
fIN7
0.4
0.5
MHz
Remark The above values are the result of NEC's evaluation of the device. If the device is likely to be affected by noise in your application, it is recommended to use the device at a voltage higher than the above values.
Data Sheet U12920EJ1V0DS00
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PD178F098
Flash Memory Programming Characteristics (VDD = 3.5 to 5.5 V, TA = 10 to 40C) (1) Write/delete characteristics
Parameter Write current (VDD pin)Note Write current (VPP pin)Note Delete current (VDD pin)Note Delete current (VPP pin)Note Unit delete time Total delete time Number of overwrite VPP power supply voltage Symbol tDDW IPPW IDDE IPPE tER tERA CWRT VPP0 VPP1 Delete and write are counted as one cycle In normal mode At flash memory programming 0 9.7 10.0 Conditions When VPP = VPP1, fX = 6.3 MHz When VPP = VPP1, fX = 6.3 MHz When VPP = VPP1, fX = 6.3 MHz When VPP = VPP1 0.5 1 MIN. TYP. MAX. 23 20 23 100 1 20 20 0.2 VDD 10.3 Unit mA mA mA mA s s times V V
Note
AVDD current and Port current (current flowing to internal pull-up resistor) are not included.
Remark fX: System clock oscillation frequency (2) Serial write operation characteristics
Parameter VPP setup time VPP setup time from VDD RESET setup time from VPP VPP count start time from RESET Count execution time VPP counter high-level width VPP counter low-level width VPP counter noise elimination width Symbol tPSRON tDRPSR tPSRRF tRFCF tCOUNT tCH tCL tNFW 8.0 8.0 40 VPP high voltage VPP high voltage VPP high voltage Conditions MIN. 1.0 1.0 1.0 1.0 2.0 TYP. MAX. Unit
s s s s
ms
s s
ns
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Data Sheet U12920EJ1V0DS00
PD178F098
Flash Write Mode Setting Timing
VDD VDD 0V VPPH VPP VPP VPPL tPSRON tPSRRF tCOUNT VDD RESET (input) 0V tCL tDRPSR tRFCF tCH
Data Sheet U12920EJ1V0DS00
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PD178F098
8. PACKAGE DRAWING
100-PIN PLASTIC QFP (14x20)
A B
80 81
51 50
detail of lead end S CD Q R
100 1
31 30
F G H I
M
J
P
K S N S L M
NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15+0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX.
P100GF-65-3BA1-4
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Data Sheet U12920EJ1V0DS00
PD178F098
9. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Table 9-1. Soldering Conditions for Surface-Mount Type
PD178F098GF-3BA: 100-pin plastic QFP (14 x 20)
Recommended Conditions Symbol IR35-00-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 sec max. (210C min.), Number of times: 3 max.
VPS
Package peak temperature: 215C, Time: 40 sec max. (200C min.), Number of times: 3 max.
VP15-00-3
Wave soldering
Solder bath temperature: 260C max., Time: 10 sec max., Number of times: 1, Preheating temperature: 120C max., (Package surface temperature) Pin temperature: 300C max., Time: 3 sec max (per device side)
WS60-00-1
Partial heating
-
Caution Do not use two or more soldering methods in combination (except partial heating).
Data Sheet U12920EJ1V0DS00
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PD178F098
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for development of systems using the PD178078 and 178098 subseries. Language processor software
RA78K/0Notes 1, 2, 3 CC78K/0Notes 1, 2, 3 DF178098Notes 1, 2, 3 CC78K0-LNotes 1, 2, 3 Assembler package common to 78K/0 series C compiler package common to 78K/0 series Device file for PD178078 subseries and PD178098 subseries C compiler library source file common to 78K/0 series
Flash memory writing tools
Fashpro III (Part number: FL-PR3Note 4, PG-FL3) FA-100GF-3BANote 4 Dedicated flash programmer
Flash programmer adapter
Debugging tools * When in-circuit emulator IE-78K0-NS is used
IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PA IE-70000-98-IF-C In-circuit emulator common to 78K/0 series Power supply unit for IE-78K0-NS Performance board for enhancing and expanding the IE-78K0-NS function Interface adapter necessary when PC-9800 series (except notebook type) is used as host machine (C bus supported) PC card and interface cable necessary when a notebook-type PC is used as host machine (PCMCIA socket supported) Interface adapter necessary when a IBM PC/ATTM compatible machine is used as host machine (ISA bus supported) Interface adapter necessary when a PC with a PCI bus is used as host machine Emulation board to emulate PD178078 and 178098 subseries Emulation probe for 100-pin plastic QFP (GF-3BA type) Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type) System simulator common to 78K/0 series Integrated debugger common to 78K/0 series Device file for PD178078 subseries and PD178098 subseries
IE-70000-CD-IF-A
IE-70000-PC-IF-C
IE-70000-PCI-IF IE-178098-NS-EM1 NP-100GFNote 4 EV-9200GF-100 SM78K0Notes 1, 2 ID78K0-NSNotes 1, 2 DF178098Notes 1, 2, 3
Notes 1. PC-9800 series (Japanese WindowsTM) based 2. IBM PC/AT compatible machine (Japanese/English windows) based 3. HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM, SolarisTM) based, NEWSTM (NEWS-OSTM) based 4. Products of Naito Densei Machida Mfg. Co., Ltd. (Tel: 044-822-3813). Remark Use the RA78K0, CC78K0, and SM78K0 in combination with the DF178098.
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Data Sheet U12920EJ1V0DS00
PD178F098
* When in-circuit emulator IE-78001-R-A is used
IE-78001-R-A IE-70000-98-IF-C In-circuit emulator common to 78K/0 series Interface adapter necessary when PC-9800 series (except notebook type) is used as host machine (C bus supported) Interface adapter necessary when IBM PC/AT compatible machine is used as host machine (ISA bus supported) Interface adapter necessary when a PC with a PCI bus is used as host machine Interface adapter and cable necessary when EWS is used as host machine Emulation board to emulate PD178078 and 178098 subseries Emulation probe conversion board necessary when using IE-178098-NS-EM1 on IE-78001-R-A Emulation probe for 100-pin plastic QFP (GF-3BA type) Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type) System simulator common to 78K/0 series Integrated debugger common to 78K/0 series Device file for PD178078 subseries and PD178098 subseries
IE-70000-PC-IF-C
IE-70000-PCI-IF IE-78000-R-SV3 IE-178098-NS-EM1 IE-78K0-R-EX1 EP-78064GF-R EV-9200GF-100 SM78K0Notes 1, 2 ID78K0Notes 1, 2 DF178098Notes 1, 2, 3
Real-time OS
RX78K/0Notes 1, 2, 3 MX78K0Notes 1, 2, 3 Real-time OS for 78K/0 series OS for 78K/0 series
Notes 1. PC-9800 series (Japanese Windows) based 2. IBM PC/AT compatible machine (Japanese/English windows) based 3. HP9000 series 700 (HP-UX) based, SPARCstation (SunOS, Solaris) based, NEWS (NEWS-OS) based Remark Use the SM78K0 in combination with the DF178098.
Data Sheet U12920EJ1V0DS00
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PD178F098
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Documents
Title Document No. Japanese English U12885E This document U12790E U12326E U12704E U14458E
PD178076, 178078, 178096, 178098 Data Sheet PD178F098 Data Sheet PD178078, 178098 Subseries User's Manual
78K/0 Series User's Manual - Instruction 78K/0 Series Application Note 78K/0, 78K/0S Series Flash Memory Write Application Note Basics (I)
U12885J U12920J U12790J U12326J U12704J U14458J
Development Tool Documents (User's Manual)
Title RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language CC78K0 C Compiler Operation Language IE-78001-R-A IE-78K0-NS IE-178098-NS-EM1 EP-78064 SM78K0 System Simulator Windows Based SM78K Series System Simulator Reference External Parts User Open Interface Specifications Reference Reference Guide Reference Operation U11517J U11518J U14142J U13731J U14013J EEU-934 U10181J U10092J U11517E U11518E To be prepared U13731E U14013E EEU-1469 U10181E U10092E U11802J U11801J U11789J Document No. Japanese English U11802E U11801E U11789E
ID78K0 Integrated Debugger EWS Based ID78K0 Integrated Debugger PC Based ID78K0 Integrated Debugger Windows Based ID78K0-NS Integrated Debugger Windows Based
U11151J U11539J U11649J U12900J U14379J
-- U11539E U11649E U12900E To be prepared
Caution The contents of the above documents are subject to change without notice. Please ensure that the latest versions are used in design work, etc.
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Data Sheet U12920EJ1V0DS00
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Related Documents for Embedded Software (User's Manual)
Document No. Title Japanese 78K/0 Series Real-time OS Fundamental Installation 78K/0 Series OS MX78K0 Fundamental U11537J U11536J U12257J English U11537E U11536E U12257E
Other Documents
Document No. Title Japanese SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Guides on NEC Semiconductor Devices NEC Semiconductor Device Reliability and Quality Control Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Device Quality/Reliability Handbook Microcomputer Product Series Guide X13769X C10535J C11531J C10983J C11892J C12769J U11416J C10535E C11531E C10983E C11892E -- -- English
Caution The contents of the above documents are subject to change without notice. Ensure that the latest versions are used in design work, etc.
Data Sheet U12920EJ1V0DS00
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PD178F098
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Purchase of NEC I 2C components conveys a license under the Philips I2 C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
IEBus is a trademark of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
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Data Sheet U12920EJ1V0DS00
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U12920EJ1V0DS00
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PD178F098
* The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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